例句與造句

1. Floating point operations were available using a single 72-bit accumulator.
2. The CPU had sixty-four 64-bit registers and another four 64-bit accumulators.
3. The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register.
4. The IMP-16 provided four 16-bit accumulators, two of which could be used as index registers.
5. Most of the Orion's instruction set used a three-address form, with sixty-four 48-bit accumulators.
6. It's difficult to find bit accumulator in a sentence. 用bit accumulator造句挺難的
7. The address is computed as the sum of the 8-bit accumulator and a 16-bit register ( PC or DPTR ).
8. The single 48-bit accumulator was fundamentally subtractive, addition being carried out by subtracting the ones'complement of the number to be added.
9. Where the 56K grouped two 24-bit data and one 8-bit extension accumulator, the 96K groups three 32-bit registers into a 96-bit accumulator.
10. The CPU has an 8-bit accumulator and 15-bit PC . 16 additional 8-bit registers ( R0 R15 ) and an 8-bit program status word are memory mapped.
11. For example, the Motorola 56000 DSP chip uses 24-bit word sizes, 24-bit multipliers and 56-bit accumulators to perform multiply-accumulate operations on two 24-bit samples without overflow or rounding.
12. Other tubes stored the single 80-bit accumulator ( A ), the 40-bit " multiplicand / quotient register " ( MQ ) and eight " B-lines ", or index registers, which was one of the unique features of the Mark 1 design.
13. The main features of the MCS-296 family is 50 MHz operation, MCS-96 compatibility, pipeline architecture, 6 MB addressable space, 2 KB code / data RAM, 40-bit accumulator, fast hardware multiplier and accumulator, and 512 Byte register RAM.
14. It shares 64 KB of PSRAM with the 6502 microprocessor family, but includes additional instructions, including XCN ( eXChange Nibble ), which swaps the upper and lower 4-bit portions of the 8-bit accumulator, and an 8-by-8-to-16-bit multiply instruction.
15. The processor is MIPS-based modified instructions, the main VU0 core is a superscalar, in-order 2-issue design with 6 stage long integer pipelines and 15 stage long floating point pipeline, 32 entries 128 bit VLIW SIMD registers ( naming / renaming ), one 64 bit accumulator and two entries 64 bit general data register, 8 entries 16 bit fix function registers and 16 entries 8 bit controller registers, two 64 bit integer ALUs, 128bit Load-Store Unit ( LSU ), Branch Execution Unit ( BXU ) and a 32 bit VU1 FPU coprocessor ( acted as sync controller for VPU0 / VPU1 ) that contain a MIPS base processor core with 32 entries 64bit FP registers and 15 entries 32bit integer registers.